Drive SOC Assembly and design chip level functions for SOCs.
Responsible for front-end design quality/correctness checks, reviews and driving those with multi-functional teams.
Drive SOC execution across chip milestones working with all multi-functional teams to help define, track and drive complex dependencies.
Define and develop system-level methodologies, tools, and IPs to build SOCs in an effective and scalable manner.
Identify difficulties and inefficiencies in the front-end chip implementation process and propose and implement ideas to solve them.
Skills & Experience
4+ years of proven experience in chip design,
specializing in SOC integration and design automation. Padring and fuse/floorsweep design experience is a bonus.
Experience in RTL design (Verilog), System-On-Chip design/implementation flow.
Solid coding skills in Perl, Python, or other industry-standard scripting languages.
Exposure to various Chip Design Functions to be able to collaborate and solve complex multi-functional problems.
Background in SOC Verification, Synthesis, Physical design and DFT is a bonus.
Experience in RTL Build flows and Makefiles is a plus.
Excellent analytical and problem-solving skills.
📌 Rtl Design Engineer Hyderabad (India)
🏢 Clarus Advisers
📍 India
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