Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design
Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
Responsible for on-time delivery of block-level layouts with acceptable quality.
Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
Guide junior team-members in their execution of Sub block-level layouts & review their work
Contribute to effective project-management.
Effectively communicating with Global engineering teams to assure the success of layout project.
Job Requirements :
- 4-20 years of experience in Analog Layout Design Engineering with a focus on CMOS processes.
- Solid understanding of DRC/LVS principles and their application in digital designs.
- Proficiency in Mentor Graphics tools (e.g., Calibre) for layout creation and verification.
- Experience working with FinFET devices and their unique characteristics.