Bangalore, KarnatakaChennai, Tamil Nadu
Job Summary

Min 5 to 7+ years of FPGA or IP/SoC architecture verification experience
Experience working in IP or ARM/RISC-V processor subsystem
Valuable understanding on different peripheral interface and AXI/APB protocol
Experience in creating verification test plan and test case in SV-UVM / C
Experience in methodology driven SoC verification - IP level minimum
Experience in fault injection simulation at IP level minimum

Key Responsibilities

Experience in creating the fault list and test case developmnet for fault injection simulation
Experience in fault injection simulation methodology (using Synopsys Z01X or Cadence or Siemens Mentor)
Able to interface with design and Functional Safety team
Experience in Perl/Python scripting.

Skill Requirements





Experience in performing safety analysis IP level
Experience in performing the design FMEA/FMEDA
Understanding on Functional Safety ISO 26262 process

Other Requirements

Min 5 to 7+years of FPGA or SoC architecture design and implementation/integration experience
Experience working in IP or IP subsystem
Good understanding on different peripheral interface and AXI/APB protocol
Good understanding on Functional Safety ISO 26262 basic concept

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📌 Senior Design Lead (India)
🏢 HCLTech
📍 India