Bangalore, Karnataka
Job Summary

Define ASIC/SoC verification strategy Positive understanding of ASIC/SoC life cycle Full chip testplan development Has participated in multiple ASIC/SoC verification till tapeout stage Full chip TB Architecture definition Experience writing ASIC/SoC testplans UVM based testbench development 1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM). SV functional coverage, Assertions coding 1.Expertise & hands-on experience in OVM/UVM methodologies using SV 2.Experience to Write, execute, and debug constra

Key Responsibilities
1. To leverage design expertise to ensure that software and products exhibit user-friendliness, intuitiveness, and alignment with user expectations,



contributing to the creation of seamless user experiences.
2. To lead a team of designers, provide guidance, and ensuring the delivery of high-quality design solutions in alignment with the overall business goals.
3. To present design concepts and play a crucial role in shaping the overall design vision and strategy.
4. To stay abreast of industry trends, emerging technologies to drive innovation and excellence in design.

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📌 Senior Design Lead (India)
🏢 HCLTech
📍 India