Senior RTL Design EngineerLocation:HyderabadExperience:3–6 YearsRole OverviewWe are looking for aSenior RTL Design Engineerwith strong hands-on expertise inEthernet-based SoC/IP design, RTL development, and design quality checks.Key ResponsibilitiesDevelop and integratesynthesizable RTLfor complex SoC/IP designs.Strong hands-on experience withEthernet protocols/IPand high-speed networking designs.Translatemicroarchitecture specifications into efficient RTL .PerformLint, CDC/RDC and RTL quality checksusingSpyGlass .Debug and resolve RTL, CDC, lint and functional issues.Collaborate with Architecture, DV, STA and Physical Design teams.Drive RTL optimization forPPA, timing,



area and power .Core Technical SkillsStrongVerilog/SystemVerilog RTL designexperience.Solidmicroarchitecture understandingand ability to work from specifications.Strong Ethernet knowledge —MAC/PCS/PHY, 10G/25G/100G/400Gexposure preferred.Hands-on experience withSpyGlass Lint & CDC .Robust understanding ofCDC, reset architecture, clocking and RTL coding practices .Experience withsynthesis, timing and PPA optimization .Strong debugging and problem-solving skills.Ideal Candidate:A hands-on RTL engineer with strongEthernet + Microarchitecture + Lint/CDC + SpyGlassexpertise and experience delivering production-quality SoC/IP designs.

📌 Senior Rtl Design Engineer (Maharashtra)
🏢 Leadsoc Technologies
📍 Maharashtra