Among. The top 4 IT companies, in India ranked by market capitalization and revenueASIC RTL LeadBangalopre / Hyderabad / KochiExperience-11+ yearsMandatory Skill : (RTL Design, RTL Coding & Integration, RTL quality checks (Lint, CDC), IP, targeted for SOC, Static checks, Protocols - PCIe, DDR, Ethernet,I2C, UART, SPI)Senior ASIC Engineer (IP RTL design targeted for SOC, Static checks, some basic protocols)Expertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System VerilogIn depth knowledge on RTL quality checks (Lint, CDC)Knowledge of synthesis and low power is a plusGood understanding of AMBA bus protocols (AXI, AHB, ATB, APB)Positive understanding of timing conceptsKnowledge of one or more of the interface protocolsa. PCIeb. DDRc. Ethernetd. I2C, UART,



SPIExpertise in setting up and using tools likea. Spyglass Lint/CDCb. Synopsys DCc. Verdi/XcelliumUnderstanding of scripting languages like Make flow, Perl ,shell, python etcUnderstanding of processor architecture and/or ARM debug architecture is a plusAble to help and debug issues for multiple subsystemsAble to create/review design documents for multiple subsystemsAble to support physical design, verification, DFT and SW teams on design queries and reviewsSkillsSoCPCIeDDREthernetLPDDRVerilogSystemVerilogXcelliumCPUARMRISC-VCon tactUdaymuday_bhaskar@yahoo .ComMulya Technologies "Mining the Knowledge Commun ity "

📌 Asic Rtl Design Lead (Maharashtra)
🏢 Mulya Technologies
📍 Maharashtra