Perform analog timing verification for critical paths using circuit‑level and mixed‑signal simulations Develop and maintain analog timing testbenches, measurement environments, and simulation setups (e.g., MRUN‑based flows) Execute simulations across PVT corners to validate setup/hold margins, pulse widths, skew, and other critical timing metrics Analyze waveforms and measurement results to identify timing violations, race conditions, and marginal behavior Debug timing‑related failures and collaborate with Design teams to determine root cause and corrective actions Review design schematics, timing intent, and specifications to ensure verification coverage of critical scenarios Develop and maintain timing verification plans, including corner selection and coverage strategy Support gate‑level and netlist‑based simulations with timing and parasitics as required Contribute to improvement of analog timing verification methodologies, flows, and automation Document verification results, assumptions, and known limitations clearly for downstream teams Bachelor's or Master's degree in Electrical Engineering,



Computer Engineering, or related field Experience in analog or mixed‑signal verification, timing analysis, or circuit validation Strong understanding of CMOS circuit design fundamentals and timing behavior Hands‑on experience with analog simulation tools (e.g., HSPICE, PrimeSim, FineSim, SpectreFx or equivalent) Familiarity with digital simulation (Verilog/SystemVerilog) and mixed‑signal environments Ability to analyze complex waveforms and perform detailed timing debug Robust problem‑solving, analytical, and communication skills Experience with DRAM or high‑speed memory circuits Exposure to dynamic timing verification beyond STA (e.g., race conditions, analog effects, clock interactions) Familiarity with gate‑level simulations, parasitic effects, and initialization behavior Scripting or programming experience (e.g., Python) for automation and data analysis Experience working in cross‑functional, global teams

📌 STAFF ENGINEER , DPG GRAPHICS VERIF (Hyderabad)
🏢 Recognized
📍 Hyderabad