Responsible for front end implementation of high speed Mixed Signal IPs and Analog intensive ASICs which includes synthesis, LEC, Low power flows, prelayout STA and postlayout STA/Timing closure Collaborate with Design, DV and PD teams to achieve closure. Highly experienced in synthesis, LEC, Low Power flows and timing closure Proven ability to understand a current mixed signal complex IP with minimal design team help and achieve synthesis to timing closure with 1st time silicon success. Handling blocks with complex designs, high frequency clocks and complex clocking complete understanding of timing constraints including asynchronous designs and DFT Have debug experience to solve issues scripting and automation Working knowledge of low power designing involving multiple power domains Should be able to identify and meet requirements for critical paths of multi-GHz designs The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams M.S./M.Tech, BS/BE (Electronics) Experience Required: 6+ Years

📌 Staff Engineer - ASIC STA (Bengaluru)
🏢 Important Business
📍 Bengaluru