Desired candidate should have a good understanding on RTL2GDS flows and methodologies. As CAD engineer he/she should have deeper understanding on how to deliver flows to design teams that enable RTL2GDS flows. Deliver methodology and tool solutions for static timing closure and power optimization . Deploy cutting-edge modeling and optimization approaches to achieve globally optimal targets .Prudently apply best-in-class algorithms and ECO techniques for value-adding design solutions . Pursue deep analysis of timing paths and power inefficiencies to isolate key issues . Implement code infrastructure to facilitate analytics and visualization . Collaborate with silicon design, CAD, and EDA partners to identify flow deficiencies and enact creative remedies Typically requires 10+ years of hands on experience in static timing analysis or PNR or RTL2GDS methodologies.



Familiar with STA or PNR or Synthesis of large high-performance in Memory technologies Strong analytical skills and ability to identify high ROI opportunities. Proven software engineering background and experience with C++, Python, Tcl programming languages. Solid understanding of cross-talk, variation, and margining. Good communicator who can accurately assess, describe issues to management and follow solutions through to completion. Familiarity with timing and power ECO techniques and implementation is a plus Familiarity with TSMC based designs will be an added plus Leading IP delivery project will be a additional plus

📌 Principal Engineer - CAD (Hyderabad)
🏢 Nameless
📍 Hyderabad