Senior Physical Design Engineer

Experience: 5–12 Years

Location: Bengaluru

Role Overview

We are looking for a hands-on Senior Physical Design Engineer with strong expertise in full-chip physical design and extensive experience with Cadence Innovus. The role involves driving physical implementation from netlist to signoff for advanced SoC designs.

Key Responsibilities

- Own full-chip physical design from floorplanning through placement, CTS, routing and signoff.
- Strong hands-on expertise with Cadence Innovus for implementation and optimization.
- Perform floorplanning, power planning, placement, CTS, routing and physical optimization.
- Drive timing closure across setup/hold, congestion, power and signal integrity.
- Work closely with STA, RTL, synthesis, DFT and IP teams to resolve implementation issues.
- Debug and optimize timing, congestion, IR/EM and physical design violations.
- Support ECO implementation and signoff closure across multiple modes/corners.
- Analyze and resolve full-chip integration issues including macro placement,



blockages, clocking and routing challenges.
- Contribute to methodology, flow automation and physical design quality improvements.

Required Skills

- 5–12 years of hands-on Physical Design experience.
- Strong full-chip SoC physical implementation experience.
- Excellent hands-on experience with Cadence Innovus.
- Strong understanding of Floorplanning, Placement, CTS, Routing and ECOs.
- Solid expertise in STA, timing closure, congestion optimization and physical verification.
- Experience with MCMM implementation and signoff.
- Robust understanding of advanced-node physical design challenges.
- Scripting experience in Tcl/Python/Perl is highly desirable.
- Strong debugging, ownership and cross-functional collaboration skills.

Preferred: Experience with high-performance CPU/SoC designs, advanced technology nodes and complex multi-clock/multi-voltage designs.

📌 Senior Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru