– Senior / Lead DFT Engineer

Position: Senior / Lead DFT Engineer

Domain: VLSI / Semiconductor

Experience: 10+ Years

Employment Type: Permanent / Contract Deployment

Location: Bengaluru / Hyderabad / India – Based on Project Requirement

Customer: Semiconductor Engineering Organization

Role Overview

We are looking for an experienced Senior / Lead Design for Test (DFT) Engineer with 10+ years of hands-on experience in DFT architecture, implementation, verification and silicon test readiness for complex ASIC/SoC designs.

The candidate should have strong experience in Scan, ATPG, MBIST, LBIST, JTAG and DFT verification , along with the ability to independently handle DFT activities from architecture through implementation and sign-off.

Key Responsibilities

- Define and implement DFT architecture and methodology for complex ASIC/SoC designs.
- Perform scan insertion, scan compression and scan-chain optimization .
- Develop and execute ATPG patterns for stuck-at, transition and other fault models.
- Perform Memory BIST (MBIST) architecture, insertion and verification.
- Work on Logic BIST (LBIST) implementation and validation where applicable.
- Implement and validate JTAG / IEEE 1149.x boundary scan architecture.
- Perform DFT rule checks and resolve DFT violations.
- Analyze and improve fault coverage and test coverage .
- Perform pattern generation, simulation, debugging and verification.
- Support gate-level simulation and timing-aware DFT validation .
- Debug scan-chain, ATPG, MBIST and pattern-related failures.
- Work closely with RTL Design, Design Verification, Physical Design, STA and Validation teams .
- Support DFT activities across the complete RTL-to-GDSII flow .
- Participate in design reviews and provide recommendations for improving testability.
- Support silicon bring-up, diagnosis and production-test related debugging .
- Mentor junior DFT engineers and provide technical guidance to the project team.




- Coordinate with customer and cross-functional engineering teams for DFT deliverables, schedules and technical closure.

Required Technical Skills

- 10+ years of hands-on DFT experience in ASIC/SoC development.
- Robust expertise in:
- Scan Insertion
- Scan Compression
- ATPG
- MBIST
- LBIST
- JTAG / Boundary Scan
- DFT Verification
- Fault Simulation & Coverage Analysis
- Pattern Generation and Validation
- Good understanding of SoC architecture, RTL design and digital design fundamentals .
- Strong understanding of clocking, reset, power domains and low-power DFT considerations .
- Experience working with large and complex multi-clock/multi-power-domain SoCs.
- Knowledge of Verilog/SystemVerilog .
- Good scripting skills in TCL, Perl and/or Python .
- Strong debugging and problem-solving capabilities.

DFT Tools Hands-on experience with one or more industry-standard DFT toolsets is expected, such as:

- Siemens Tessent
- Synopsys TestMAX / DFTMAX
- Cadence Modus

Experience with simulation, synthesis, STA and related semiconductor design tools will be an advantage.

Preferred Experience

- DFT architecture ownership at SoC/subsystem level .
- Experience with advanced technology nodes.
- Hierarchical DFT implementation.
- Low-power DFT methodology.
- ATPG coverage improvement and pattern optimization.
- Memory repair/BISR implementation.
- Silicon diagnosis and yield-debug support.
- Experience leading or mentoring a team of DFT engineers.
- Customer-facing experience in semiconductor engineering programs.

Educational Qualification B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, ECE, VLSI, Microelectronics or an equivalent engineering discipline.

Candidate Profile The ideal candidate should be capable of independently owning DFT activities for a complex ASIC/SoC program , working with cross-functional engineering teams and driving DFT implementation through verification, sign-off and silicon support.

Interested candidates may share their updated resume with:

Clock Edge Technologies Pvt. Ltd. (CET)

Email: [email protected]

Contact: +91 98842 15701

📌 Senior / Lead DFT Engineer (Bangalore Metropolitan Area)
🏢 CLOCK EDGE TECHNOLOGIES PRIVATE
📍 Bangalore Metropolitan Area