Rtl design engineer (Asifnagar)

Rtl design engineer (Asifnagar)

21 Aug
|
JobCrexa
|
Asifnagar

21 Aug

JobCrexa

Asifnagar

Job Title - RTL Design Engineers

Exp Level: 4+ yrs

Loctaion: Hyderabad /Bangalore

- RTL coding knowledge
- Top-level (SOC) level basic industry standard Arch knowledge
- So C & IP level Integration knowledge
- IPXACT knowledge
- IORING and Phys & GPIOs basic functionality
- Design Partitioning(Tilification) knowledge
- Design RTL quality checks:

Clock domain crossing(CDC)

Reset domain crossing(RDC)

LINT

VSI

UPF knowledge

LEC(Logic equivalence check)

Timing concepts & SDC knowledge
- Tools knowledge:

Vc_static or equivalent other tools(VSI) VC_spyglass LINT, CDC and RDC

0in

Formality and conformal LEC tool

- Design and scripting languages:

Verilog and SV

Perl

Python

TCL

Interested can share CV to sharmila.b@

📌 Rtl design engineer (Asifnagar)
🏢 JobCrexa
📍 Asifnagar

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