Job Title - RTL Design Engineers /n Exp Level: 4+ yrs /n Loctaion: Hyderabad /Bangalore /n : /n • RTL coding knowledge /n • Top-level (SOC) level basic industry standard Arch knowledge /n • SoC & IP level Integration knowledge /n • IPXACT knowledge /n • IORING and Phys & GPIOs basic functionality /n • Design Partitioning(Tilification) knowledge /n • Design RTL quality checks: /n /n
- Clock domain crossing(CDC)
/n
- Reset domain crossing(RDC)
/n
- LINT
/n
- VSI
/n
- UPF knowledge
/n
- LEC(Logic equivalence check)
/n
- Timing concepts & SDC knowledge
/n /n • Tools knowledge: /n /n
- Vc_static or equivalent other tools(VSI)
/n
- VC_spyglass LINT, CDC and RDC
/n
- 0in
/n
- Formality and conformal LEC tool
/n /n • Design and scripting languages: /n /n
- Verilog and SV
/n
- Perl
/n
- Python
/n
- TCL
/n /n /n Interested can share CV to
[email protected]
📌 RTL Design Engineer (Hyderabad)
🏢 ACL Digital
📍 Hyderabad