21 Aug
|
Infobell IT Solutions
|
Bengaluru
21 Aug
Infobell IT Solutions
Bengaluru
Roles and Responsibilities :
- Design, develop, test, and verify complex digital circuits using Verilog/VHDL languages for FPGA implementation.
- Collaborate with cross-functional teams to integrate ASIC designs into larger systems.
- Develop and maintain RTL code for high-speed interfaces such as PCIe, DDR memory controllers, and USB protocols.
- Troubleshoot issues in existing designs by analyzing simulation results and debugging techniques.
Job Requirements :
- 5-10 years of experience in designing FPGAs using Verilog/VHDL languages.
- Solid understanding of ASIC design principles and methodologies (RTL coding).
- Proficiency in developing RTL code for various interfaces including PCIe, DDR memory controllers, and USB protocols.
📌 FPGA Engineer (Bengaluru)
🏢 Infobell IT Solutions
📍 Bengaluru