Job DescriptionSenior RTL Design Engineer
nLocation: Hyderabad
nExperience: 3–6 Years
nRole Overview
nWe are looking for a Senior RTL Design Engineer with strong hands-on expertise in Ethernet-based SoC/IP design, RTL development, and design quality checks.
nKey Responsibilities
n
- n
- Develop and integrate synthesizable RTL for complex SoC/IP designs.n
- Strong hands-on experience with Ethernet protocols/IP and high-speed networking designs.n
- Translate microarchitecture specifications into efficient RTL.n
- Perform Lint, CDC/RDC and RTL quality checks using SpyGlass.n
- Debug and resolve RTL, CDC, lint and functional issues.n
- Collaborate with Architecture, DV, STA and Physical Design teams.n
- Drive RTL optimization for PPA, timing, area and power.n

nCore Technical Skills
n
- n




- Solid Verilog/SystemVerilog RTL design experience.n
- Solid microarchitecture understanding and ability to work from specifications.n
- Strong Ethernet knowledge — MAC/PCS/PHY, 10G/25G/100G/400G exposure preferred.n
- Hands-on experience with SpyGlass Lint & CDC.n
- Strong understanding of CDC, reset architecture, clocking and RTL coding practices.n
- Experience with synthesis, timing and PPA optimization.n
- Strong debugging and problem-solving skills.n

nIdeal Candidate: A hands-on RTL engineer with strong Ethernet + Microarchitecture + Lint/CDC + SpyGlass expertise and experience delivering production-quality SoC/IP designs.

📌 Senior RTL Design Engineer (Hyderabad)
🏢 Leadsoc Technologies
📍 Hyderabad