Job ID 2026-17835 Date posted Aug. 21, 2026 Location Bengaluru, India Category Hardware Engineering, Design Engineering
Role Summary
Our Solutions Engineering Physical IP team comprises some of the industry’s leading experts in deep submicron circuit design. This position is a wonderful opportunity for you to work with our custom standard cell design engineering team on cutting-edge technologies. Your work will have a significant lasting impact as the designs will be used in Solutions Engineering products servicing the infrastructure, client, automotive, and IoT market segments.
Key Responsibilities
- Layout design of logic standard cells (inverters, muxes, flops cells, complex logic gates) optimized for performance, area, and power.
- Work with automation and QA teams to support library validation flows.
- Collaborate with circuit designers to understand schematics and translate them into clean, compact layouts.
- Drive design rule clean (DRC) and layout vs. schematic (LVS) closure using industry-standard verification tools (e.g., Calibre ).
- Perform layout debugging and root-cause analysis for DRC, LVS, and other physical sign-off issues.
- Handle cell abutment, cell profiling, and cell integration constraints for logic libraries.
- Address layout-dependent effects (LDE) and double patterning/EUV compliance in advanced nodes.
- Review and debug standard cell physical views (LEF, GDS, abstract views) for integration into digital flows.
- Automate layout QA, regression checks, and PDK-driven layout verifications using scripts (e.g., SKILL, Python).
- Participate in library quality audits and delivery cycles including signoff package creation and documentation.
Required Skills and Experience
- 3+ years of custom layout experience in logic standard cell development.
- Proven track record of working at 5nm, 3nm, or 2nm nodes with FinFET/GAA-based technologies.
- Proficiency in Cadence Virtuoso.
- Deep understanding of advanced DRC rules, LVS methodologies, and multi
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