Senior Rtl Design Engineer (Bommasandra)

Senior Rtl Design Engineer (Bommasandra)

22 Aug
|
Optics & Allied Engg-( Optica
|
Bommasandra

22 Aug

Optics & Allied Engg-( Optica

Bommasandra

Location: Bangalore (Bommasandra)
Experience: 3-4 Years
Employment Type: Full time

Position Overview

Key Responsibilities
- Design, develop, and implement FPGA-based digital logic using VHDL and/or Verilog HDL.
- Design and implement Image and Video Processing Pipelines on FPGA.
- Develop FPGA interfaces for ADC (Analog-to-Digital Converter) and DAQ (Data Acquisition) systems.
- Design and integrate FFT, DSP, filtering, and signal processing blocks.
- Implement and optimize Memory Interfaces (DDR3/DDR4, SRAM, BRAM, FIFO, etc.).
- Develop and integrate AXI4/AXI-Stream Interconnects and high-speed communication interfaces.
- Perform Clock Domain Crossing (CDC) analysis and implement robust synchronization techniques.
- Achieve FPGA Timing Closure through constraint optimization and design improvements.
- Perform FPGA synthesis, implementation, debugging, and validation.
- Bring up FPGA designs on development boards and perform hardware debugging using logic analyzers and on-chip debugging tools.
- Collaborate with hardware, firmware, embedded software,



and system engineering teams during product development.
- Prepare design documentation, verification reports, and technical specifications.
- Participate in design reviews and support system integration activities.

Required Qualifications
- Bachelor's or Master's Degree in Electronics & Communication Engineering, Electrical Engineering, Embedded Systems, Computer Engineering, or a related field.
- 3-4 years of experience in FPGA/RTL Design and Digital Hardware Development.

Technical SkillsMandatory Skills
- Strong RTL coding experience using VHDL and/or Verilog:
- FPGA development using AMD/Xilinx or Intel (Altera) FPGA devices
- Hands-on experience with ADC and DAQ interface development:
- Core FPGA architecture and module development
- Image and Video Processing Pipeline implementation
- FFT and DSP block implementation
- Memory Interface development (DDR, SRAM, FIFO, BRAM)
- AXI4, AXI4-Lite, and AXI-Stream Inter

📌 Senior Rtl Design Engineer (Bommasandra)
🏢 Optics & Allied Engg-( Optica
📍 Bommasandra

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