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JOB Descrption:
BE/BTECH/ME/MTECH
EXP:1-4 and Relavant
Pre/Post Silicon validation
Defines, develops, and performs functional validation for integrated SoCs, focusing on validation of IP integration, interaction between IPs, and system level features.
Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met
Reviews proposed design changes to assess impact on validation plans, tasks, and timelines
Develops SoC validation methodologies, validation test plans, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis
Performs silicon debug to identify root causes and resolves all functional and triage failures for SoC issues. Tests interactions between various SoC features using validation infrastructure
Develops postsilicon validation infrastructure (e.g., performance monitors, behavioral checkers,



state space coverage) and test workplace used in validation testing
Works with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for SoC interfaces and to meet desired product specifications
Develops content to create or increase specific IP interactions using a variety of tools and techniques (including patching techniques using microcode, firmware, or custom OS builds)
Engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (e.g., simulation, emulation, FPGAs) to ensure silicon readiness
BE/BTech/Diploma in Electronics and Communications Engineering with 4+ years of experience
Knowledge of CPU Architectures like RISC-V, x86 and ARM
Knowledge of PCIe Express, UART, I2C, SPI, USB, Ethernet, NoC (Network on a Chip),

📌 Design Engineer I (Hyderabad)
🏢 Cadence Design Systems
📍 Hyderabad