Senior Formal Verification Engineer

Location: Bangalore
Experience: 8–10 Years
Employment Type: Full-time

Job Summary

We are hiring a Senior Formal Verification Engineer for one of our leading clients. The candidate will be responsible for formal verification of complex IPs and subsystems.

Key Responsibilities
- Develop and verify formal properties for complex designs.
- Perform Formal Property Verification (FPV) and connectivity verification.
- Work on architectural and formal sign-off activities.
- Analyze proof convergence and debug verification issues.
- Collaborate with RTL, design, and verification teams.

Required Skills
- Solid experience in Formal Verification / FPV
- SystemVerilog, SVA, UVM
- Experience with Cadence JasperGold or Synopsys VC Formal




- Knowledge of DDR, PCIe, or Ethernet
- Knowledge of AMBA – AXI / AHB / APB
- Experience in formal connectivity and architectural verification

Good to Have
- SerDes / PHY verification experience
- UPF and low-power formal verification
- Experience mentoring junior engineers

How to Apply

Interested candidates can share their updated CV.

[email protected] / (phone hidden)

If you have any relevant references, please feel free to share them with us.

Pay: ₹3,000,000.00 - ₹5,000,000.00 per year

Work Location: In person

📌 Senior Formal Verification Engineer (Bengaluru)
🏢 Org Linked
📍 Bengaluru