Job Title: Senior DFT Engineer

Experience Level: 10+ Years

Work Location: Bangalore, India

Domain: VLSI / Semiconductor / ASIC Design

Employment Type: Full-Time

Position Overview:

We are seeking an experienced and self-driven Senior DFT (Design for
Testability) Engineer with 10+ years of hands-on experience to lead and
execute block-level and chip-level DFT architecture, implementation,
pattern generation, and sign-off. The ideal candidate will possess
deep expertise in scan insertion, ATPG, timing analysis, and
industry-standard EDA tools, along with robust cross-functional
coordination skills to drive high-quality silicon testability.

Key Roles & Responsibilities:

DFT Implementation & Architecture:

Lead end-to-end DFT activities at both Block level and Chip level,
including Scan insertion, compression setup, and boundary scan
integration.
Define and implement DFT modes, constraints, and timing sign-off protocols.
ATPG & Pattern Generation:

Develop and deliver ATPG patterns across various fault models,
including Stuck-at (Nominal and VBOX), IDDQ,



and Transition/At-Speed
faults.
Analyze fault coverage metrics and implement strategies to drive
continuous coverage improvement.
Validation & Timing Sign-off:

Perform pattern validation with and without timing (Gate-Level
Simulations / GLS) to ensure zero failure rates prior to tape-out.
Perform DFT mode timing analysis, setup/hold fixing, and formal
verification/sign-off.
Cross-Functional Collaboration:

Partner closely with RTL Integration, Synthesis, Static Timing
Analysis (STA), and Physical Design teams to identify, debug, and
resolve cross-functional dependencies and timing bottlenecks.
Post-Silicon & Advanced Architecture (Desirable):

Support MBIST (Memory Built-In Self-Test) design and integration.
Assist in post-silicon bring-up, silicon debug, and failure analysis
for test-related issues.

Required Qualifications & Technical Skills:

Education & Experience

Education: Bachelor's or Master's degree in

📌 senior DFT Engineer (Bengaluru)
🏢 HappieHire
📍 Bengaluru