SRAM Memory Design Engineer

Role: Memory Design Engineer – SRAM

Key responsibilities
Design and develop SRAM memory macros for ASIC/SoC technologies.
Design and analyze 6T/8T/10T SRAM bitcells, sense amplifiers, write drivers, precharge circuits, decoders, and peripheral circuits.
Perform schematic design, simulation, characterization, and optimization across PVT corners.
Analyze SRAM for read stability, write margin, leakage, speed, power, and area.
Develop and optimize memory architectures for different capacity, performance, and power requirements.
Work on low-voltage SRAM operation and variation/Monte Carlo analysis.
Collaborate with layout, circuit verification, PDK, and physical design teams.
Support memory compiler/macro development, silicon characterization, and debug.




Perform post-layout simulations and resolve design issues.
Document design methodology, specifications, simulation results, and silicon correlation.

Typical qualifications
B.E./B.Tech or M.E./M.Tech in Electrical/Electronics/VLSI.
Robust understanding of CMOS transistor-level circuit design.
Knowledge of SRAM architecture and memory circuits.
Experience with Cadence Virtuoso/Spectre or equivalent tools.
Understanding of SPICE simulation, PVT, Monte Carlo, mismatch, and process variation.
Knowledge of semiconductor fundamentals, timing, power, and signal integrity.
Familiarity with Linux, scripting (Perl/Python/Tcl), and automation is often practical.

📌 Memory Design Engineer Bengaluru
🏢 Aritrak Technologies
📍 Bengaluru