Physical Design Engineer Job Description

Role: Physical Design / Backend VLSI Engineer

Key Responsibilities
Perform complete RTL-to-GDSII physical design flow for ASIC/SoC designs.
Work on floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
Analyze and optimize timing, power, area (PPA).
Perform STA and resolve setup/hold timing violations.
Handle congestion, IR drop, electromigration (EM), and signal integrity issues.
Perform ECO implementation and timing/area optimization.
Run and debug DRC, LVS, antenna, ERC, and other physical verification checks.
Work with synthesis, STA, DFT, RTL, and custom-design teams to resolve implementation issues.
Generate and review GDSII/OASIS, DEF, LEF, SPEF, and other implementation data.
Support block-level and/or full-chip physical design and tapeout activities.

Required Skills
Robust understanding of CMOS/VLSI physical design fundamentals.
Valuable knowledge of:
Floorplanning
Placement
CTS
Routing
Timing closure
Power optimization




Physical verification
Hands-on experience with tools such as:
Synopsys ICC2 / Fusion Compiler
Cadence Innovus
Synopsys PrimeTime
StarRC
Calibre
Knowledge of SDC constraints, timing paths, clock definitions, false paths, multicycle paths, etc.
Understanding of UPF/low-power design is an advantage.
Scripting knowledge in Tcl, Python, or Perl is highly desirable.
Familiarity with Linux/Unix environments.

Typical Qualifications
B.E./B.Tech/M.E./M.Tech in Electrical, Electronics, VLSI, or related fields.
Experience can range from fresher/entry-level to senior physical design engineer, depending on the position.

Key Interview Topics

For a Physical Design interview, focus especially on:
Floorplan and power planning
Placement and congestion
CTS and clock skew
Setup and hold timing
Timing optimization
Routing and SI/crosstalk
IR drop and EM
DRC/LVS
MMMC/PVT corne

📌 Physical Design Engineer Bengaluru
🏢 Aritrak Technologies
📍 Bengaluru