Job DescriptionRole Overview:
n

nAs an ASIC Design Engineer, you will play a key role in microarchitecture definition, RTL design, and implementation of high-speed interface IPs. You will collaborate with cross-functional teams to deliver high-performance, power-effective, and scalable silicon solutions.
n

nKey Responsibilities:
n

n
n
Experience 10+yrs , Bangalore locationn
Architect and design high-performance ASIC SoCs, targeting high-speed protocols such as PCIe Gen4/5, 100G/400G Ethernet, USB3/4, SerDes-based interfaces.n
Develop RTL using Verilog/System Verilog with a focus on performance, power, and area (PPA) optimizationn
Define and document micro-architecture and interface specifications for protocol IPsn
Collaborate with verification teams to develop test plans, debug failures, and achieve coverage closuren
Work closely with physical design teams on synthesis, timing closure, and floor planning supportn
Analyze and debug silicon bring-up issues related to high-speed interfacesn
Integrate third-party IPs (SerDes, PHYs)



and ensure proper functionality and interoperabilityn
Participate in design reviews and ensure adherence to design methodologies and best practicesn
Drive design quality through lint, CDC, and verification readiness checksn

n

nRequired Skills:
n

n
n
Solid experience in RTL design using Verilog/System Verilog.n
Deep understanding of high-speed protocols, such as: PCIe (Gen4/Gen5), Ethernet (100G/400G), USB (USB3/USB4), SerDes-based architectures.n
Solid background in microarchitecture design and trade-off analysisn
Experience in SoC integration and subsystem designn
Valuable knowledge of synthesis, STA, and physical design considerationsn

n

nGood to Have:
n

n
n
Experience in silicon bring-up and post-silicon debugn
Exposure to advanced technology nodes and high-frequency designsn
Scripting skills (Python/Perl/Shell) for automationn

n

nWhat We’re Looking For:

📌 Rtl Design Jharkhand (India)
🏢 SmartSoC Solutions
📍 India