- M.S or equiv. degree and 3 years experience
- Job entails and requires experience in Design and verification using C/C++, Verilog HDL, VCS, Pearl timing analysis, Cadence Buildgates.
- Implementing and mapping of PCI-Express core interface on Xilinx Virtex-II FPGA.
- Synthesizing using synplify tool, any two of the following protocols/domains:
RapidIO, Gigabit Ethernet and SONET
- Relocation within USA Possible
- Email your resume to [email protected] with Job Code – TDM in the subject line.