Qualification: Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field
Role Overview
We are looking for a Physical Verification / Layout Verification Engineer with hands-on experience in VLSI physical verification and layout signoff activities. The candidate will be responsible for running and debugging physical verification checks and supporting block/IP-level signoff and tape-out.
Key Responsibilities
- Perform VLSI layout physical verification and signoff activities.
- Run and debug DRC, LVS, ERC, Antenna, and Density checks.
- Analyze and resolve LVS shorts, opens, device mismatches, connectivity issues, and rule violations .
- Work with Siemens Calibre or equivalent physical verification tools.
- Understand and debug issues related to CMOS layout and device extraction .
- Ensure layouts comply with foundry design rules and technology requirements .
- Support block/IP-level physical verification, signoff, and tape-out activities.
- Develop or use scripts for verification automation using Perl, Python, Shell, or TCL .
- Collaborate with layout, design, and other verification teams to close physical verification issues.
Required Skills
- 3+ years of experience in VLSI Layout Verification / Physical Verification .
- Strong hands-on experience with:
- DRC
- LVS
- ERC
- Antenna checks
- Density checks
- Solid experience with Siemens Calibre or equivalent PV tools.
- Good understanding of CMOS layout, device extraction, and foundry design rules .
- Experience debugging LVS shorts, opens, device mismatches, and connectivity issues .
- Scripting knowledge in Perl / Python / Shell / TCL .
- Experience supporting signoff and tape-out activities.