? Hiring: Lead PCIe Verification Engineer | 7+ Years | Bangalore & Hyderabad
Are you an experienced Design Verification Engineer ready to take ownership of complex SoC/IP verification and lead verification activities? ?
We’re looking for talented Lead Verification Engineers with 7+ years of experience to join our growing semiconductor engineering team in Bangalore & Hyderabad .
? Key Responsibilities
PCIE gen 5 and 6
• Lead IP/SoC-level Design Verification activities from planning to sign-off
• Define verification strategy, test plans and coverage goals
• Develop and maintain SystemVerilog/UVM-based verification environments
• Drive functional, constrained-random and assertion-based verification
• Debug complex simulation failures and perform root-cause analysis
• Own coverage closure — code, functional and assertion coverage
• Work closely with RTL Design, Architecture, Emulation and Post-Silicon teams
- Review testbench architecture, test cases, assertions and verification results
- Mentor junior/mid-level verification engineers
- Track verification milestones,
risks and deliverables
?️ Must-Have Skills
✅ 7+ years of experience in Design Verification
✅ Strong SystemVerilog & UVM expertise
✅ Hands-on experience with SoC/IP verification
✅ Strong understanding of functional coverage & code coverage
✅ Experience in constrained-random verification
✅ Valuable knowledge of SVA / Assertions
✅ Strong debugging skills using simulation and waveform tools
✅ Experience with AMBA protocols — AXI/AHB/APB/ACE
✅ Scripting/programming knowledge in Python / Perl / C/C++
✅ Ability to lead verification tasks and mentor engineers