Among. The top 4 IT companies, in India ranked by market capitalization and revenue

nASIC RTL Lead

nBangalopre / Hyderabad / Kochi

nExperience-11+ years

nMandatory Skill : (RTL Design, RTL Coding & Integration, RTL quality checks (Lint, CDC), IP, targeted for SOC, Static checks, Protocols - PCIe, DDR, Ethernet,I2C, UART, SPI)

nSenior ASIC Engineer (IP RTL design targeted for SOC, Static checks, some basic protocols)

nnExpertise in SoC subsystem/IP design

nExpertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog

nIn depth knowledge on RTL quality checks (Lint, CDC)

nKnowledge of synthesis and low power is a plus

nGood understanding of AMBA bus protocols (AXI, AHB, ATB, APB)

nGood understanding of timing concepts

nKnowledge of one or more of the interface protocols

na. PCIe

nb. DDR

nc. Ethernet

nd. I2C, UART, SPI





nExpertise in setting up and using tools like

na. Spyglass Lint/CDC

nb. Synopsys DC

nc. Verdi/Xcellium

nUnderstanding of scripting languages like Make flow, Perl ,shell, python etc

nUnderstanding of processor architecture and/or ARM debug architecture is a plus

nAble to help and debug issues for multiple subsystems

nAble to create/review design documents for multiple subsystems

nAble to support physical design, verification, DFT and SW teams on design queries and reviews

nnSkills

nSoC

nPCIe

nDDR

nEthernet

nLPDDR

nVerilog

nSystemVerilog

nXcellium

nCPU

nARM

nRISC-V

nn Con tact

nUday

nmuday_bhaskar@yahoo .com

n Mulya Technologies

n"Mining the Knowledge Commun ity"

📌 ASIC RTL Design Lead (Ernakulam)
🏢 Mulya Technologies
📍 Ernakulam