Among. The top 4 IT companies, in India ranked by market capitalization and revenue /n ASIC RTL Lead /n Bangalopre / Hyderabad / Kochi /n experience-11+ years /n Mandatory Skill : (RTL Design, RTL Coding & Integration, RTL quality checks (Lint, CDC), IP, targeted for SOC, Static checks, Protocols - PCIe, DDR, Ethernet,I2C, UART, SPI) /n Senior ASIC Engineer (IP RTL design targeted for SOC, Static checks, some basic protocols) /n /n Expertise in SoC subsystem/IP design /n Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog /n In depth knowledge on RTL quality checks (Lint, CDC) /n Knowledge of synthesis and low power is a plus /n Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) /n Positive understanding of timing concepts /n Knowledge of one or more of the interface protocols /n a. PCIe /n b.

DDR /n c. Ethernet /n d. I2C, UART,



SPI /n Expertise in setting up and using tools like /n a.

Spyglass

Lint/CDC /n b. Synopsys DC /n c. Verdi/Xcellium /n Understanding of scripting languages like Make flow, Perl ,shell, python etc /n Understanding of processor architecture and/or ARM debug architecture is a plus /n Able to help and debug issues for multiple subsystems /n Able to create/review design documents for multiple subsystems /n Able to support physical design, verification, DFT and SW teams on design queries and reviews /n /n Skills /n SoC /n PCIe /n DDR /n Ethernet /n LPDDR /n Verilog /n SystemVerilog /n Xcellium /n CPU /n ARM /n RISC-V /n /n Con tact /n Uday /n muday_bhaskar@yahoo .com /n Mulya Technologies /n "Mining the Knowledge Commun ity"

📌 ASIC RTL Design Lead (Hyderabad)
🏢 Mulya Technologies
📍 Hyderabad