Meta's Silicon Engineering team is building custom silicon solutions that power the infrastructure behind Meta's AI and data center workloads. As an engineer focused on implementation, you may drive the physical realization of complex custom chips from RTL through tapeout, working across synthesis, place-and-route, timing closure, and signoff. In this role, you will work on power modeling for ASICs (architecture to silicon), developing flows around EDA tools, and low-power design to build effective System on Chip (SoC) and IP for data center applications. You will collaborate with architecture, design, and verification teams to deliver high-performance, power-efficient silicon that meets aggressive PPA targets for Meta's next-generation infrastructure platforms.

ASIC Engineer, Implementation [Low-Power Design] Responsibilities:
Define the power specification at system and module level for Idle, TDP, Typical use cases
Develop power modeling infrastructure in Python/C++
Work with or develop architectural simulators in order to model performance and power




Build power estimation flows at various levels of abstraction: C-model, RTL, Gate, Layout
Apply knowledge of ASIC design processes, including leakage and agile power, to evaluate the impact of setting and manufacturing process on power
Understand system level concepts and optimize design for low-power
Evaluation and Implementation of low-power design techniques at different levels of abstraction
Collaborate with RTL designers to identify and resolve timing, area, and power issues early in the design cycle
Participate in design reviews and provide implementation feedback to influence upstream architectural and microarchitectural decisions
Power characterization on silicon: idle, TDP, use case power
debug power issues on silicon
Partner with vendors to drive low-power requirements for SoC interfaces such as LPDDR, PCIe, etc. Partner with EDA tool vendors to select and deploy the appropriat

📌 Asic Engineer, Implementation Bengaluru (India)
🏢 Meta
📍 India