Static Timing Analysis (Bengaluru)

Static Timing Analysis (Bengaluru)

24 Aug
|
leadIC Design
|
Bengaluru

24 Aug

leadIC Design

Bengaluru

Static Timing Analysis (STA) Engineer

Company:
leadIC Design Pvt Ltd

Location:
Bengaluru, Karnataka, India

Work Mode:
Hybrid

Employment Type:
Full-time

About the Role

leadIC Design Pvt Ltd is looking for experienced
Static Timing Analysis (STA) Engineers
to work on
timing analysis, timing closure, and signoff
for ASIC/SoC designs.

This role is specifically focused on
Static Timing Analysis (STA) and timing signoff
. We are looking for candidates with hands-on STA experience rather than general VLSI or Physical Design experience.

Key Responsibilities
- Perform
Static Timing Analysis (STA)
for block-level and/or full-chip ASIC/SoC designs.
- Analyze and close
setup and hold timing violations
.
- Perform
timing signoff
across multiple modes and PVT/RC corners.
- Develop, validate, and debug
SDC (Synopsys Design Constraints)
.
- Perform
MMMC (Multi-Mode Multi-Corner)
timing analysis.
- Analyze
clock latency, clock skew, uncertainty, jitter, and clock paths
.
- Perform timing analysis using
Synopsys PrimeTime and/or Cadence Tempus
.
- Analyze
OCV, AOCV, POCV, LVF,



and CRPR/CPPR
effects.
- Debug timing issues caused by
parasitics, routing, crosstalk, and signal integrity
.
- Perform
timing ECOs
and work with Physical Design teams for timing closure.
- Analyze
WNS, TNS, critical paths, path groups, and timing reports
.
- Work with
SPEF, RC corners, extracted parasitics, and signoff libraries
.
- Develop STA automation and reporting using
Tcl/Python/Perl
where required.

Required Experience
- Hands-on experience specifically in
Static Timing Analysis (STA)
.
- Experience in
STA signoff and timing closure
.
- Strong knowledge of
setup/hold analysis
.
- Hands-on experience with
PrimeTime and/or Tempus
.
- Solid understanding of
SDC constraints
.
- Experience with
MMMC/MCMM analysis
.
- Understanding of
PVT, RC corners, OCV/AOCV/POCV
.
- Experience debugging timing violations and performing
timing ECOs
.
- Understanding of
clock timing, CTS, skew, latency, and uncerta

📌 Static Timing Analysis (Bengaluru)
🏢 leadIC Design
📍 Bengaluru

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