Key Tasks / Responsibilities

- Design Architecture and micro-architecture development

- RTL Coding (Verilog, VHDL/System Verilog language)

- Power management implementation

- CDC, Lint

- Design implementation on FPGA

- Ability to create and develop micro-architecture design specifications for the given block /IP.

- RTL design experience and development with Verilog/VHDL/System Verilog language

- Perform block /Unit level verification along with CDC and linting checks.

- GLS capabilities with SDF annotation run at specified corners

- Synthesis, STA with Timing closure and work closely with functional verification and Physical Design teams for closure and clean handover

- Scripting skills with shell/perl/python

- Working knowledge in complex ASIC/FPGA environment with custom/embedded MCU and SoC architectures

- Working knowledge with Automotive, DSP, Image and Display processing architectures.





- Working with Low Power design architectures and ability to support for UPF/LPF or power-aware simulations

- Understanding /Working Knowledge of formal verification concepts and support verification team.

Key skills / Background

- 15+ years of RTL design experience.

- Familiar with Digital Signal processing is an add-on.

- Able to micro-architect the blocks and code.

- Verilog, VHDL and System Verilog.

- Excellent communication and problem-solving skills.

- Should have experience working in geographically dispersed teams and should be a robust team player.

Personal Skills

- Excellent communication and interpersonal skills

- Self motivated

- Take ownership of problems

- Creative problem solving

- Strong and effective presentation skills, able to operate at multiple levels including senior management

- Team player

📌 RTL Design Engineer (India)
🏢 Chiplogic Technologies
📍 India