Senior Design Verification Engineer / Lead
Location: Bangalore | Hyderabad | Ahmedabad | Pune | Noida | Chennai
Experience: 5 to 15 Years

Job Description
We are seeking experienced Design Verification Engineers to join our Semiconductor Engineering team and contribute to the verification of complex ASIC and SoC designs. The ideal candidate should possess robust expertise in SystemVerilog, UVM, and advanced verification methodologies, along with hands-on experience in developing scalable verification environments and driving verification closure.

Key Responsibilities
Develop and maintain robust UVM-based SystemVerilog verification environments.
Create and execute verification plans for Block, Subsystem, and SoC-level verification.
Develop testbenches, assertions, checkers, scoreboards, and functional coverage models.
Drive verification closure through coverage analysis, debugging, and regression management.
Collaborate closely with RTL, DFT, Physical Design, and Architecture teams.
Review design specifications and ensure comprehensive verification of functional requirements.




Participate in technical reviews, customer interactions, and project planning activities.
Mentor junior engineers and contribute to process and methodology improvements.

Required Skills
Strong hands-on experience in SystemVerilog and UVM.
Experience with OVM/VMM and industry-standard verification methodologies.
Expertise in assertion-based verification and functional coverage.
Hands-on experience in ASIC/SoC Verification projects.
Strong debugging and problem-solving skills.
Knowledge of verification tools and regression management flows.
Experience with one or more industry-standard protocols:
PCIe, NVMe, DDR, Ethernet, USB, MIPI, NAND, CPU Subsystems

Preferred Qualifications
Experience leading verification projects or teams.
Customer-facing experience and technical ownership of projects.
Understanding of complete ASIC/SoC development lifecycle.

Educational Qualification
Bachelor's or Maste

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