Job Summary

Project description. The ideal candidate will develop high-quality RTL, drive IP/subsystem integration, and ensure design readiness through rigorous quality checks including Lint, CDC, RDC, synthesis, and handoff validation.

Responsibilities

- Own RTL development from architecture interpretation through design handoff, including IP integration, clock/reset handling, address mapping, and configuration.
- Perform detailed RTL reviews and quality assessments, identifying and driving closure of functional, structural, and methodology issues.
- Analyze and resolve Lint, CDC/RDC, X-propagation, synthesis, and structural violations, collaborating with architecture, design, and verification teams.
- Ensure RTL handoff readiness through clean signoffs, protocol compliance,



register-spec alignment, and clock/reset architecture validation.
- Build and enhance design automation and quality methodologies, including automated checks, regression analysis, dashboards, and team-level quality gates.

Skills Must have
- Verilog/System Verilog
- IP integration
- AMBA interfaces (AXI4, AXI4-Lite, AHB, APB)
- Lint
- CDC/RDC
- X-propagation
- Synthesis
- Design signoff
- Automation

Nice to have
- Candidates should be passionate about design quality, automation, and delivering production-ready RTL with minimal debug cycles.

📌 RTL Design Engineer (Hyderabad)
🏢 Luxoft
📍 Hyderabad