Roles & Responsibilities
Well versed in Verilog and SV with positive understanding of RTL design, verification and synthesis practices. Prior work experience in the RTL and/or gate level verification domain is a must.
Well conversant with different verification methodologies like assertion, function and test coverage with positive understanding of test generation process.
Knowledge on low power design and verification methods using UPF is a must.
Expertise in RTL quality sign-off through lint checks, IP to SoC integration, IP hand-off, constraints etc., RTL hand-off to backend.
An expert user of one or more of the following verification tools: NC-Sim, Modelsim, VCS, Specman, Debussy and/or Verdi*
Valuable automation skills in PERL and/or TCL and/or Shell*. Good communication skills (written and verbal).

Designation: Front End RTL Design Automation Engineer

Experience: 2+ years & above

Location: Bangalore/Hyderabad

Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics

Number of Positions: 5

📌 Front End Rtl Design Automation Engineer Bengaluru
🏢 pozibility technologies
📍 Bengaluru