Experience:
3+ Years

Location:
Bangalore

Education:
B.Tech/B.E./M.Tech/M.E. in VLSI, Electronics, Electrical Engineering

Job Summary:

We are looking for a
Synthesis Engineer
with hands-on experience in
Synthesis, PPA Optimization, LEC, CLP, UPF, and timing constraints
. The candidate will work closely with STA, Physical Design, DFT, and RTL teams to deliver optimized and high-quality netlists.

Key Responsibilities:
Perform
Synthesis
for complex SoC/block-level designs.
Drive
PPA (Power, Performance & Area) optimization
.
Develop, validate, and debug
SDC/MMMC constraints
.
Perform
LEC (Logic Equivalence Checking)
and debug equivalence issues.
Perform
CLP checks
and resolve constraint-related issues.
Work on
UPF/low-power flows
and validate power intent.




Analyze
timing, area, power, and QoR
reports and drive optimization.
Support
ECO implementation and timing closure
.
Collaborate with
STA, Physical Design, DFT, and RTL teams
for design closure.
Develop and maintain automation using
Tcl/Python
.

Required Skills:
3+ years of hands-on experience in
Synthesis
.
Solid knowledge of
LEC, CLP, UPF, PPA, SDC, and MMMC
.
Positive understanding of
timing, power, area, and synthesis methodologies
.
Experience with
Synopsys/Cadence synthesis tools
.
Robust debugging and problem-solving skills.

📌 Synthesis Engineer Bengaluru
🏢 Mirafra Technologies
📍 Bengaluru