Physical Design Engineer – NVIDIA / AMD Accounts

Location: Bengaluru

Experience: 3–5 Years

Employment Type: Full-Time

Pay : Its Open for Negotiate any Digit

Job Summary

We are looking for a Physical Design Engineer with 3–5 years of experience in semiconductor VLSI physical design to work on NVIDIA / AMD accounts. The role involves end-to-end block-level RTL-to-GDSII implementation, with a strong focus on PPA optimization, timing closure, and physical design quality.

Key Responsibilities

- Execute block-level RTL-to-GDSII physical design implementation.
- Perform floorplanning, power planning, placement, CTS, routing, and optimization.
- Drive static timing analysis (STA) and timing closure across multiple PVT corners.
- Analyze and resolve setup, hold, congestion, DRC, LVS, and signal integrity issues.
- Optimize designs for Power, Performance, and Area (PPA) targets.
- Perform placement and routing optimization to achieve timing and congestion targets.
- Work closely with RTL, Synthesis, STA, DFT, and Physical Verification teams.
- Debug physical design issues and implement ECOs for timing and functional closure.
- Generate and review physical design reports including timing, congestion, utilization, and QoR.
- Ensure design quality and adherence to project schedules and implementation methodologies.





Required Skills

- 3–5 years of hands-on experience in Physical Design / Backend VLSI.
- Strong understanding of RTL-to-GDSII flow.
- Hands-on experience in:
- Floorplanning
- Placement
- Clock Tree Synthesis (CTS)
- Routing
- Timing Closure
- ECO implementation
- Physical verification
- Strong understanding of STA, timing constraints, setup/hold analysis, and PVT corners.
- Experience with UPF/low-power implementation is an advantage.
- Valuable understanding of IR drop, electromigration (EM), crosstalk, congestion, and signal integrity.
- Strong scripting/programming skills in Tcl, Python, or Perl.

Tools

Experience with industry-standard EDA tools such as Synopsys ICC2 / Fusion Compiler, PrimeTime, Design Compiler or equivalent tools from Cadence.

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or a related engineering discipline.

Preferred

- Experience working on advanced technology nodes.
- Exposure to high-performance CPU/GPU/SoC designs.
- Experience supporting NVIDIA / AMD or similar high-performance semiconductor programs.
- Strong problem-solving, debugging, and analytical skills.

Pay: ₹4,000,000.00 - ₹6,000,000.00 per year

Work Location: In person

📌 Physical Design Engineer – NVIDIA / AMD Accounts (Bengaluru)
🏢 aldaa
📍 Bengaluru