- Required Experience:
- 3-7 yrs
- Location:
- Delhi-NCR
- Openings
- 5-8
- Education
- BE/ BTech (Electronics/ Electrical/ Electronics and Communication) MS or MTech would be preferred
The candidate is expected to have worked on :
- Scan insertion and DRC cleanup
- Pattern generation for Stuck-At, delay test, iddq, path delay and fault grading.
- Memory testing. Should also know the algorithms. Should also have knowledge about diagnostics.
- JTAG or P1500 or other interface mechanism
Desirable competencies
The candidate is expected to have exposure to :
- Compression tools is highly desirable
- LBIST, mixed-signal testing, logic equivalence
- Writing testbenches and should be capable of writing RTL code for DFT blocks as and when required.
- Bridge fault detection is desirable
- ATE experience is an added advantage
Email your resume to
[email protected] and mention position/location in the subject.
📌 Senior DFT Engineer (Delhi)
🏢 Truechip Solutions
📍 Delhi