Job Description ID- JDAS016

Location : Hyderabad/Bangalore (In office)

Overview

Responsible for verifying high-performance, safety-compliant IPs in accordance with industry standards such as ISO 26262.

Key Responsibilities

IP Verification & Functional Safety Compliance :

Develop and execute verification test plans for safety-critical semiconductor IPs using UVM/SystemVerilog.
Ensure verification methodologies comply with FuSa requirements per ISO 26262/IEC 61508 and industry best practices.

Safety Mechanisms & Testbench Development

Verify safety mechanisms such as ECC, CRC, watchdog timers, and redundancy techniques.
Develop UVM-based testbenches, test cases, and constrained-random stimulus for IP-level verification.

Testbench Development & Failure Analysis

Develop UVM-based testbenches, test cases, and constrained-random stimulus for IP-level verification.
Collaborate with safety architects to perform FMEDA (Failure Modes, Effects, and Diagnostic Analysis)



and other safety assessments.

Collaboration & Documentation

Work cross-functionally with design engineers, safety teams, and system architects to ensure compliance with safety and performance requirements.
Generate verification reports, safety work products, and support safety certification processes.

Required Skills & Experience

Strong proficiency in SystemVerilog/UVM for verification of ASIC/FPGA designs
Hands-on experience with safety-critical IP verification and fault injection methodologies..
Familiarity with FMEDA, FTA (Fault Tree Analysis), and safety verification concepts.
Experience with functional coverage, assertion-based verification, and code coverage analysis.
Understanding of ISO 26262, IEC 61508, or DO-254 safety standards.
Expertise in EDA tools (Synopsys, Cadence, Mentor Graphics).

📌 Functional Safety IP Verification (Hyderabad)
🏢 AISEMI PRIVATE
📍 Hyderabad