? We are Hiring: Silicon Design Engineer – CAD (PPA Regression & Front-End Flow)
ACL Digital is looking for a skilled CAD Engineer with 3–5 years of experience to join our team in Hyderabad. In this role, you will build scalable PPA regression infrastructure, support RTL-to-Gate synthesis flows (DC/Genus), and automate metric tracking across advanced technology nodes. If you excel at Python/Tcl scripting, Unix environments, and driving flow efficiency for timing, area, and power, we want to hear from you!