25 Aug
|
Leadsoc Technologies
|
Hyderabad
25 Aug
Leadsoc Technologies
Hyderabad
Senior Memory Design Engineer /n Experience- (4–8 Years) /n Location: Hyderabad /n About the Role /n Join a high-performance silicon engineering team developing next-generation SRAM and memory IP for advanced SoCs. You will drive memory architecture, circuit design, characterization, and silicon optimization to deliver high-speed, low-power, and robust memory solutions across leading-edge process technologies. /n Key Responsibilities /n /n
- Design and optimize SRAM and memory circuits for performance, power, area, and yield.
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- Develop memory building blocks including bitcells, sense amplifiers, write drivers, row/column decoders, precharge circuits, redundancy, and peripheral logic.
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- Perform transistor-level design, simulation, and verification across PVT corners, Monte Carlo, noise, and reliability analyses.
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- Drive post-layout verification (PEX) and collaborate with layout teams for optimal matching and manufacturability.
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- Support silicon bring-up, characterization, failure analysis, and yield improvement.
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- Work closely with architecture, physical design, DFT,
and product engineering teams throughout the memory development lifecycle.
/n /n Required Qualifications /n /n
- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, or related discipline.
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- 4–8 years of hands-on experience in SRAM or memory circuit design.
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- Solid understanding of CMOS device physics, transistor-level design, memory architecture, stability, and reliability.
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- Proficiency with Cadence Virtuoso, Spectre, ADE XL/Assembler, and extraction tools such as Calibre xRC/StarRC.
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- Experience with post-layout simulation, PEX, LVS/DRC, EM/IR, and silicon correlation.
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- Scripting experience in Python, SKILL, Perl, or TCL is a plus.
/n /n Preferred Experience /n /n
- Experience with advanced process nodes (FinFET technologies).
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- Exposure to high-performance CPU, GPU, AI Accelerator, Networking, or Data Center SoCs.
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- Knowledge of low-voltage memory design, yield optimization, and low-power techniques.
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📌 Senior Memory Design Engineer (Hyderabad)
🏢 Leadsoc Technologies
📍 Hyderabad