Company Description The company is an engineering-focused organization committed to developing high-quality products and solutions for global markets. It offers a collaborative environment where design, innovation, and rigorous technical standards are valued. Team members work closely across disciplines to turn complex requirements into reliable, scalable designs.

The organization emphasizes qualified growth, continuous learning, and the use of modern design tools and methodologies. Joining the team provides opportunities to contribute to challenging projects with real-world impact.

Role Description

● Top 3 mandatory (primary) skills: • Verilog, system verilog, UVM

● IP level TB component development

● Mastery in EDA tools (Verdi,vcs) etc

● Good to have (secondary) skills: ● Comfortable in scripting for automation

- AI tools usage

● Experience in digital+analog verification

● Soft Skills • Converse with teams across various geographies

- Scope: Owns IP and top-level ASIC verification for complex SerDes subsystems.




- Domain: Verifies digital RTL integrated with analog behavioral models using SystemVerilog/UVM.
- Alignment: Ensures seamless functionality across digital, analog, and firmware boundaries.
- Metrics: Drives testbench architecture and test planning to achieve coverage closure.

Job Responsibilities / Day-to-Day Activities
- Spec Review: Analyze design specs and collaborate with designers to align test plans.
- Testbench Development: Build or upgrade UVM testbenches, write tests, and close coverage.
- Cross-Team Integration: Work with RTL, analog, and firmware teams to bridge design gaps and verify system-level interfaces.
- Behavioral Model Verification: Validate subsystem functionality including analog model and firmware interactions in the digital testbench.
- Productivity: Leverage approved automation and AI tools to accelerate debugging and triage.

📌 RTL Design Engineer (Bengaluru)
🏢 QuessCorp
📍 Bengaluru