? Hiring: Memory Layout Engineer | Bangalore

We are looking for a Memory Layout Engineer with 5–10 years of experience to join our semiconductor engineering team in Bangalore.

? Technology Nodes: TSMC / Samsung – 2nm, 3nm, 5nm, 7nm & GF Nodes

? Qualification: B.E./B.Tech / M.E./M.Tech in Electrical Engineering

Key Skills:

- Solid experience in SRAM/DRAM, memory compiler IPs & memory periphery
- Hands-on layout experience with bit-cell arrays, sense amplifiers, decoders, I/O & control logic
- Expertise in top-level memory integration, DRC, LVS, density verification & physical closure
- Knowledge of IR/EM challenges, FinFET design rules & DFM guidelines
- Experience with Cadence/Synopsys layout and physical verification tools
- Ability to optimize layouts for area, power, performance, yield & manufacturability
- Strong collaboration with circuit design, verification, PDK & methodology teams

? Location: Bangalore

? Experience: 5–10 Years

? Interested candidates can share their updated profile / CV.

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📌 Memory Layout Engineer | Bangalore | 5-10 Years Experience | Immediate to 15 day Notice period only (Bengaluru)
🏢 Headway Tek
📍 Bengaluru