Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
The Cadence Advantage
The opportunity to work on cutting-edge technology in an setting that encourages you to be creative, innovative, and to make an impact.
Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.
Job Summary
In this job, you will be responsible for development of Formal Verification IPs in form of a Verilog design model and System Verilog Assertions for industry standard bus protocols.
This role offers front row access to the cutting-edge innovation happening in Formal Verification and an opportunity to master a variety of protocols.
Job Responsibilities :
This Job involves development of the Assertion Based Verification IPs.
He/She should understand the designs and assertions for the formal verification.
A fair bit of automation and scripting language like Python/TCL required in this activity.
He/She should work as indiv
📌 Verification Engineer (Noida)
🏢 Cadence
📍 Noida