Job Description – Senior Analog Layout Engineer (7nm FinFET or below High-Speed Design)
Position Title
Senior Analog Layout Engineer – 7nm FinFET High-Speed Layout
Experience
5–12 Years (depending on complexity and ownership level)
Location
Kolkata / Hyderabad / Bangalore
Role Summary
We are seeking a highly skilled Senior Analog Layout Engineer with solid experience in advanced FinFET technology nodes (7nm and below) and high-speed analog/mixed-signal layout design. The ideal candidate will be responsible for translating schematics into high-quality physical layouts while ensuring compliance with foundry design rules, performance requirements, and project specifications.
The engineer will work closely with circuit designers and verification teams to develop robust layouts for high-speed analog and mixed-signal IPs, ensuring successful DRC/LVS closure and post-layout verification.
Key Responsibilities
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Create and optimize floorplans for analog and mixed-signal blocks in advanced 7nm FinFET technology.
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Translate sub-block schematics into physical layouts while maintaining hierarchy and design intent.
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Perform detailed transistor-level and block-level layout implementation for high-speed circuits.
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Ensure layout matches parameterized devices (PCells) and simulation hierarchy on a one-to-one basis.
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Follow design documentation, review comments, customer feedback, and back-annotation requirements during layout execution.
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Perform and resolve Design Rule Check (DRC) violations until the layout is fully clean.
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Perform and resolve Layout Versus Schematic (LVS) discrepancies until successful signoff.
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Ensure layouts comply with all foundry-specific design rules and reliability requirements.
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Generate extracted netlists for post-layout simulations and back-annotation activities.
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Work closely with Design Engineers (DEs) to support post-layout verification and performance closure.
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Document layout methodologies, notes, and implementation details in block review

📌 Analog Layout Engineer (Hyderabad)
🏢 Cyient
📍 Hyderabad