Own end‑to‑end IP and SOC development from micro‑architecture through RTL design, integration, and silicon support. Own IP and Subsystem design from scratch, ensuring high‑quality, reusable RTL. Drive SoC integration, including CDC, lint, synthesis, STA, and power analysis. Define and review module interfaces and system‑level architecture. Collaborate closely with Architecture, Verification, FW, DFT, Synthesis, and Physical Design teams. Provide technical mentorship and participate in design and methodology reviews. 12+ years of hands‑on IP & SoC RTL design experience. Strong expertise in micro‑architecture, Verilog/System Verilog, and RTL integration. Solid knowledge of asynchronous design concepts and CDC methodologies. Deep understanding of SoC design flows (Lint, CDC, Synthesis/STA, Power). Robust fundamentals in digital design and scripting languages. Ability to work effectively with global cross‑functional teams. Exposure to LPDDR Subsystem, CPU Subsystems, and SoC Test Controller design. Experience with ASIC controllers for storage or memory systems.

📌 Principal Engineer ASIC SoC Design (Hyderabad)
🏢 Nameless
📍 Hyderabad