Physical Design Engineer

Location: Bengaluru

Experience: 4–10 Years

Role Overview

We are looking for a hands-on Physical Design Engineer to drive implementation and timing closure for complex ASIC/SoC designs .

Key Responsibilities
Execute RTL-to-GDSII flow including synthesis, floorplanning, placement, CTS and routing.
Drive STA, MCMM timing analysis, setup/hold closure and ECOs .
Analyze and resolve congestion, IR/EM, signal integrity and physical design issues .
Optimize PPA, timing, power and area across implementation stages.
Collaborate with RTL, STA, DFT and signoff teams to achieve tapeout readiness .
Develop and enhance PD automation using Tcl/Python/Perl .

Core Technical Skills
Solid hands-on experience in ASIC Physical Design .




Expertise in floorplanning, placement, CTS, routing and timing closure .
Experience with Synopsys ICC2 / Fusion Compiler, PrimeTime, Design Compiler or equivalent.
Strong understanding of MCMM, clocking, constraints and ECO methodology .
Exposure to advanced-node designs, IR/EM and physical signoff is preferred.
Solid debugging, scripting and problem-solving skills.

Ideal Candidate: A technically solid Physical Design engineer with solid implementation and timing-closure experience, capable of owning blocks or full-chip activities through tapeout.

📌 Physical Design Engineer Bengaluru
🏢 leadsoc technologies
📍 Bengaluru