26 Aug
|
HCLTech
|
Chennai
Chennai, Tamil Nadu
Job Summary
Experience in RTL coding using Verilog/SV
Experience in design using Xilinx or Altera devices
Key Responsibilities
Experience in using Vivado or Quartus
Experience in supporting lab debug
Positive understanding of FPGA debugging techniques
2 to 5 years experience in front end design
Skill Requirements
Experience in CDC/Linting/Tool Flow
Experience with ASIC/SoC development flow including synthesis/Timing Constraints development is preferred
Other Requirements
Experience in RTL Synthesis
Scripting experience is preferable
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📌 Designer (Chennai)
🏢 HCLTech
📍 Chennai