26 Aug
|
Blueberry Semiconductors
|
Bengaluru
26 Aug
Blueberry Semiconductors
Bengaluru
Location: Bangalore
Location: 1-15 Years
Preferred Education
- Any Degree is fine
Area of Expertise
- Experienced in RTL design using Verilog / System Verilog
- ASIC designers with experiences in all aspects of RTL design flow from Specification/Microarchitecture definition to design and verification, Timing Analysis, DFT and Implementation
- Integration, RTL signoff tools, UPF/Low power signoff and CDC/RDC, Lint
- Strong domain knowledge of Clocking, System modes, Power management, debug, interconnect, safety, security, and other architectures
- Highly motivated, self-starter with positive interpersonal skills and a strong team player
- Excellent communication, critical thinking, and problem-solving skills
📌 RTL ASIC Engineer (Bengaluru)
🏢 Blueberry Semiconductors
📍 Bengaluru