Execute device matching, symmetry, common centroid, shielding, guard rings, and parasitic-sensitive layout techniques.Work on technology nodes 28nm, 40nm, 55nm, 65nm, 90nm, 130nm, 180nm, or above.Perform and resolve DRC, LVS, ERC, and antenna violations.Collaborate closely with circuit designers to optimize layout for performance, area, and yield.Support post-layout verification and parasitic extraction activities.Ensure layouts comply with foundry design rules and reliability requirements.Participate in tape-out activities and silicon bring-up support when required.