Job Description:Work as a member of a geographically distributed verification team to verify next-generation ASIC and FPGAsDevelop testplans, implement testbenches, create testcases, and ensure functional coverage closureHandle regression testing and contribute to verification infrastructure developmentDevelop both directed and random verification testsDebug test failures, identify root causes, and work with RTL and firmware engineers to resolve design defects and test issuesReview functional and code coverage metrics, modify or add tests or constrain random tests to meet coverage requirementCollaborate with design, software and architecture teams to verify design under test
Preferred Experience:Proficient in IP-level FPGA and ASIC verificationKnowledge of PCIe, CXL or other IO protocol is preferredProficient in Verilog/SystemVerilog,
and scripting languages such as Perl or PythonHands-on experience with SystemVerilog and UVM is mandatoryExperience in developing UVM-based verification testbenches, processes, and flowsSolid understanding of design flow, verification methodology, and general computational logic design and verification
About CompanyACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.
📌 Verification Lead (Mumbai)
🏢 ACL Digital
📍 Mumbai
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